Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst4|altpll_component|auto_generated 2 0 0 0 5 0 0 0 0 0 0 0 0
inst4 1 0 0 0 1 0 0 0 0 0 0 0 0
inst|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
inst|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
inst|rst_controller 33 30 0 30 2 30 30 30 0 0 0 0 0
inst|irq_mapper 7 27 2 27 32 27 27 27 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_012|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_012 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_011 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_010 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_009 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_008 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_006 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 22 1 2 1 21 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter_001 22 0 0 0 21 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_cmd_width_adapter 128 3 0 3 105 3 3 3 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_rsp_width_adapter|uncompressor 44 4 0 4 35 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_rsp_width_adapter 110 3 0 3 123 3 3 3 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux_001|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux_001|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux_001 247 0 0 0 124 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux|arb|adder 52 26 0 26 26 26 26 26 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux|arb 17 0 4 0 13 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|rsp_mux 1589 0 0 0 135 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_012 126 4 2 4 245 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_011 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_010 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_009 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_008 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_007 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_006 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_005 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_004 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_003 126 4 2 4 245 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_002 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux_001 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|rsp_demux 125 1 2 1 123 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_012|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_012|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_012 247 0 0 0 124 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_011 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_010 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_009 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_008 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_007 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_006 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_005 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_004 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_003|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_003|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_003 247 0 0 0 124 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_002 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux_001 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_mux 125 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|cmd_demux_001 138 4 13 4 245 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|cmd_demux 149 169 2 169 1587 169 169 169 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter 107 3 5 3 105 3 3 3 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_burst_adapter 107 0 0 0 105 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_instruction_master_limiter 248 0 0 0 258 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_data_master_limiter 248 0 0 0 258 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_014|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_014 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_013|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_013 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_012|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_012 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_011|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_011 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_010|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_010 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_009|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_009 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_008|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_008 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_007|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_007 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_006|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_006 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_005|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_005 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_004|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_004 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_003|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_003 94 0 2 0 105 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_002|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
inst|mm_interconnect_0|router_002 112 0 2 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router_001|the_default_decode 0 17 0 17 17 17 17 17 0 0 0 0 0
inst|mm_interconnect_0|router_001 112 0 6 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|router|the_default_decode 0 17 0 17 17 17 17 17 0 0 0 0 0
inst|mm_interconnect_0|router 112 0 6 0 123 0 0 0 0 0 0 0 0
inst|mm_interconnect_0|sdram_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sdram_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|sdram_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_1_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_1_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|key_1_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_2_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_2_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|key_2_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_3_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|key_3_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|key_3_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|switches_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|switches_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|switches_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|red_leds_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|red_leds_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|red_leds_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sys_clk_timer_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sys_clk_timer_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|sys_clk_timer_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|green_leds_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|green_leds_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|green_leds_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|onchip_memory_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|onchip_memory_s1_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sysid_control_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sysid_control_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|sysid_control_slave_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_agent_rdata_fifo 63 41 0 41 20 41 41 41 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_agent_rsp_fifo 134 39 0 39 93 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_agent 242 22 34 22 257 22 22 22 0 0 0 0 0
inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent 310 39 50 39 328 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_instruction_master_agent 196 39 91 39 144 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_data_master_agent 196 39 91 39 144 39 39 39 0 0 0 0 0
inst|mm_interconnect_0|sdram_s1_translator 111 4 3 4 98 4 4 4 0 0 0 0 0
inst|mm_interconnect_0|key_1_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|key_2_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|key_3_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|switches_s1_translator 111 6 29 6 36 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|red_leds_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|sys_clk_timer_s1_translator 95 22 44 22 55 22 22 22 0 0 0 0 0
inst|mm_interconnect_0|green_leds_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|onchip_memory_s1_translator 111 7 15 7 86 7 7 7 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_debug_mem_slave_translator 111 5 19 5 82 5 5 5 0 0 0 0 0
inst|mm_interconnect_0|sysid_control_slave_translator 111 6 27 6 35 6 6 6 0 0 0 0 0
inst|mm_interconnect_0|sram_avalon_sram_slave_translator 76 5 8 5 58 5 5 5 0 0 0 0 0
inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator 111 5 30 5 70 5 5 5 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_instruction_master_translator 112 51 2 51 105 51 51 51 0 0 0 0 0
inst|mm_interconnect_0|nios_processor_data_master_translator 112 12 2 12 105 12 12 12 0 0 0 0 0
inst|mm_interconnect_0 487 0 0 0 512 0 0 0 0 0 0 0 0
inst|sysid 3 21 2 21 32 21 21 21 0 0 0 0 0
inst|sys_clk_timer 23 0 0 0 17 0 0 0 0 0 0 0 0
inst|switches 22 0 0 0 32 0 0 0 0 0 0 0 0
inst|sram 42 0 0 0 42 0 0 0 16 0 0 0 0
inst|sdram|the_niosiiSystem_sdram_input_efifo_module 66 0 0 0 66 0 0 0 0 0 0 0 0
inst|sdram 66 1 1 1 58 1 1 1 32 0 0 0 0
inst|red_leds 38 14 14 14 50 14 14 14 0 0 0 0 0
inst|onchip_memory|the_altsyncram|auto_generated 52 0 0 0 32 0 0 0 0 0 0 0 0
inst|onchip_memory 55 0 1 0 32 0 0 0 0 0 0 0 0
inst|nios_processor|cpu 0 0 0 0 0 0 0 0 0 0 0 0 0
inst|nios_processor 151 0 0 0 130 0 0 0 0 0 0 0 0
inst|key_3 39 0 31 0 33 0 0 0 0 0 0 0 0
inst|key_2 39 0 31 0 33 0 0 0 0 0 0 0 0
inst|key_1 39 0 31 0 33 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|jtag_uart 38 10 23 10 34 10 10 10 0 0 0 0 0
inst|green_leds 38 24 24 24 40 24 24 24 0 0 0 0 0
inst 23 0 0 0 75 0 0 0 48 0 0 0 0