| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| inst|irq_mapper |
4 |
30 |
2 |
30 |
32 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001 |
207 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux|arb|adder |
28 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux|arb |
11 |
0 |
4 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux |
717 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_006 |
105 |
1 |
2 |
1 |
103 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_005 |
105 |
1 |
2 |
1 |
103 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_004 |
105 |
1 |
2 |
1 |
103 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_003 |
106 |
4 |
2 |
4 |
205 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_002 |
106 |
4 |
2 |
4 |
205 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_001 |
105 |
1 |
2 |
1 |
103 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux |
105 |
1 |
2 |
1 |
103 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_006 |
105 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_005 |
105 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_004 |
105 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_003 |
207 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002 |
207 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_001 |
105 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux |
105 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_demux_001 |
112 |
4 |
7 |
4 |
205 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_demux |
117 |
49 |
2 |
49 |
715 |
49 |
49 |
49 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_instruction_master_limiter |
208 |
0 |
0 |
0 |
212 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_data_master_limiter |
208 |
0 |
0 |
0 |
212 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_008|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_008 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_007|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_007 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_006|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_006 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_005|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_005 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_004|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_004 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_003|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_003 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_002|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_002 |
98 |
0 |
2 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_001|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_001 |
98 |
0 |
5 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router |
98 |
0 |
5 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|red_leds_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|red_leds_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|red_leds_s1_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sys_clk_timer_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sys_clk_timer_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sys_clk_timer_s1_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|green_leds_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|green_leds_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|green_leds_s1_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_debug_mem_slave_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sysid_control_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sysid_control_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sysid_control_slave_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
276 |
39 |
44 |
39 |
288 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_instruction_master_agent |
164 |
37 |
71 |
37 |
130 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_data_master_agent |
164 |
37 |
71 |
37 |
130 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|red_leds_s1_translator |
99 |
6 |
17 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sys_clk_timer_s1_translator |
83 |
22 |
32 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|green_leds_s1_translator |
99 |
6 |
17 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_translator |
99 |
7 |
3 |
7 |
86 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_debug_mem_slave_translator |
99 |
5 |
7 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sysid_control_slave_translator |
99 |
6 |
15 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
99 |
5 |
18 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_instruction_master_translator |
100 |
51 |
2 |
51 |
93 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios_processor_data_master_translator |
100 |
12 |
2 |
12 |
93 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0 |
284 |
0 |
0 |
0 |
298 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|sysid |
3 |
15 |
2 |
15 |
32 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
| inst|sys_clk_timer |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|red_leds |
38 |
14 |
14 |
14 |
50 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory |
55 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios_processor|cpu |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios_processor |
151 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart|the_niosiiSystem_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|green_leds |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| inst |
2 |
0 |
0 |
0 |
26 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |