FPGA.SeanWRall.com | Lesson2
FPGA.SeanWRall.com
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Lesson 2
Starting A Project With Altera Quartus II And Creating A System With Qsys
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Documentaion | Download PDF

Creating A Project in Quartus II
  1. Open Quartus II
  2. Go to File --> New Project Wizard...
    1. Click next to the introduction screen
    2. For the working directory choose C:/altera/mySystems/system1
    3. Name the project NiosII
    4. Name the top level entity the same as the project name, in this case Nios II
    5. Click next
    6. Choose an Empty project
    7. Click next
    8. Click next to the add files (this is for importing designs into your project, but we don’t have any designs)
    9. Click next
    10. Under family choose Cyclone IV E
    11. Filter by the number written on your FPGA, for the DE2-115 it is “ep4ce115f29c7”
    12. Select your FPGA
    13. Click next
    14. Under simulation select none
    15. Click next
    16. Now you have a summary page then click finish
    17. Now you have the basic project setup

Note: You cannot have any spaces in your file path or file names

Creating a Block Diagram in Quartus II
  1. Go to File --> New
    1. Select Block Diagram/Schematic File
    2. Click Ok
  2. Save the Block digram file by going to File --> Save As
    1. Make sure you are in your working directory (in this case C:/altera/mySystems/system1)
    2. Save the block diagram the same as what you named your project
      (in this case NiosII.bdf)
    3. Click Save
Creating A Basic System In Qsys
  1. Go to Tools --> Qsys (or you can click on this ion in the task-bar)
  2. Clock
    1. Double Click on clk_0 to edit it
      1. Make sure the clock frequency is set to 50000000 Hz
      2. Exit out of the clock by clicking the X
    2. Rename the clk_0 to Clock by right clicking on the clock and choosing Rename (alternatively you can select to the clock with a single click and press F2 yon your keyboard to rename)
    3. Export clk_in by double clicking in the associated export column; name this clk
    4. Export clk_in_reset by double clicking in the associated export column; name this reset
  3. Adding The Nios II Processor
    1. In the Ip Catalog in the left hand side navigate to Processors and Peripherals --> Embedded Processors --> Nios II Processor
      1. Double clcik on the name of the component to add, or select the component and click add
    2. A Settings window swill appear
      1. Under main for Nios II core select Nios II/f
      2. Click Finish
    3. Rename the nios2_gen2_0 by right clicking on name and selecting rename, rename the processor to “nios_processor”
    4. Add the following connections by clicking on the circle to make it a filled in circle under the connections column
      1. Clock.clk connected to nios_processor.clk
      2. Clock.clk_reset connected to nios_processor.reset
      3. nios_processor.debug_reset_request connected to nios_processor.reset
      4. nios_processor.data_master connected to nios_processor.debug_mem_slave
      5. nios_processor.instruction_master connected to nios_processor.debug_mem_slave
  4. On Chip Memory
    1. Search in the top of the ip catalog to the left for “on chip” and selest the “On-Chip Memory (RAM or ROM)”
    2. Add this by double clicking it
    3. In the pop up select the following
      1. Type set to RAM (writable)
      2. Block Type set to AUTO
      3. Data width set to 32
      4. For the DE2-115 Total memory size 20400bytes (this is different per development board, consult your boards documentation)
      5. Have checked “initialize memory content”
      6. Click finish
    4. Rename the component to onchip_memory
    5. Make the following connections
      1. Clock.clk connect to onchip_memory.clk1
      2. nios_processor.data_master connect to onchip_memory.s1
      3. nios_processor.instruction_master connect to onchip_memory.s1
      4. Clock.clk_reset connect to onchip_memory.reset1
      5. nios_processor.debug_reset_request connect to onchip_memory.reset
    6. Set the base address to 0x000
    7. Lock the base address by clicking the lock icon and making it locked
    8. In the top navigation go to System --> Assign Base Addresses
  5. It is best practice to set your primary memory (the memeory you plan to run instuctions off to
    both .data_master and .instruction_master and then set all other memeory just to .data_master

  6. Jtag Uart
    1. Search in the top of the ip catalog to the left for “jtag” and select “JTAG UART”
    2. Add this by double clicking it
    3. In the pop up select the following for both Write and Read FIFO
      1. Buffer depth select 64
      2. irq threshold select 8
      3. Click finish
    4. Rename the component to jtag_uart
    5. Make the following connections
      1. Clock.clk connect to jtag_uart.clk
      2. Clock.clk_reset connec to jtag_uart.reset
      3. nios_processor.data_master connect to jtag_uart.avalon_jtag_slave
      4. ios_processor.debug_reset_request connect to jtag_uart.reset
    6. Connect the IRQ by clicking on the box in the IRQ column and set it to 8
    7. In the top navigation go to System --> Assign Base Addresses
  7. It is best practice to set the Jtag Uart IRQ to a least priority, you have 32 interrupts 0 being first priority and 32 being least priority

  8. System ID or sysID
    1. Search in the top of the ip catalog to the left for “sysid” and select “System ID Peripheral”
    2. Add this by double clicking it
    3. In the pop up create a random hex number as the system ID
      1. Click finish
    4. Rename the component to sysid
    5. Make the following connections
      1. Clock.clk connect to sysid.clk
      2. Clock.clk_reset connec to sysid.reset
      3. nios_processor.data_master connect to sysid.control_slave
      4. ios_processor.debug_reset_request connect to sysid.reset
    6. Connect the IRQ by clicking on the box in the IRQ column and set it to 8
    7. In the top navigation go to System --> Assign Base Addresses
  9. You must have a System ID of something other on 0 for the system to work in the Nios II development tools for eclipse

  10. Green LED’s PIO
    1. Search in the top of the ip catalog to the left for “pio” and select “PIO (Parallel I/O)”
    2. Add this by double clicking it
    3. In the pop up select the following
      1. Width to 8 bits
      2. Direction select Output
      3. Output Port Rest Value 0x00
    4. Rename the component to green_leds
    5. Make the following connections
      1. Clock.clk connect to green_leds.clk
      2. Clock.clk_reset connec to green_leds.reset
      3. nios_processor.data_master connect to green_leds.s1
      4. ios_processor.debug_reset_request connect to green_leds.reset
    6. Export the external connection by double clicking on the export column
      1. Name the export green_leds
    7. In the top navigation go to System --> Assign Base Addresses
  11. Save the system
  12. In the top navigation go to Generate --> Generate HDL...
    1. Choose Verilog
    2. Uncheck Create timing and resource estimates for third-party EDA synthesis tools
    3. Check Create block symbol file (.bsf)
    4. Select none for create symbol model
    5. Make sure the output path directory is the same as the project directory
    6. Click Generate
  13. Note: Before Generating there must not be any errors or warnings in Qsys



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