- Open Quartus II
- Go to File --> New Project Wizard...
- Click next to the introduction screen
- For the working directory choose C:/altera/mySystems/system1
- Name the project NiosII
- Name the top level entity the same as the project name, in this case Nios II
- Click next
- Choose an Empty project
- Click next
- Click next to the add files (this is for importing designs into your project, but we don’t have any designs)
- Click next
- Under family choose Cyclone IV E
- Filter by the number written on your FPGA, for the DE2-115 it is “ep4ce115f29c7”
- Select your FPGA
- Click next
- Under simulation select none
- Click next
- Now you have a summary page then click finish
- Now you have the basic project setup
Note: You cannot have any spaces in your file path or file names
- Go to File --> New
- Select Block Diagram/Schematic File
- Click Ok
- Save the Block digram file by going to File --> Save As
- Make sure you are in your working directory (in this case C:/altera/mySystems/system1)
- Save the block diagram the same as what you named your project
(in this case NiosII.bdf) - Click Save
- Go to Tools --> Qsys (or you can click on this ion in the task-bar)
- Clock
- Double Click on clk_0 to edit it
- Make sure the clock frequency is set to 50000000 Hz
- Exit out of the clock by clicking the X
- Rename the clk_0 to Clock by right clicking on the clock and choosing Rename (alternatively you can select to the clock with a single click and press F2 yon your keyboard to rename)
- Export clk_in by double clicking in the associated export column; name this clk
- Export clk_in_reset by double clicking in the associated export column; name this reset
- Double Click on clk_0 to edit it
- Adding The Nios II Processor
- In the Ip Catalog in the left hand side navigate to Processors and Peripherals --> Embedded Processors --> Nios II Processor
- Double clcik on the name of the component to add, or select the component and click add
- Double clcik on the name of the component to add, or select the component and click add
- A Settings window swill appear
- Under main for Nios II core select Nios II/f
- Click Finish
- Rename the nios2_gen2_0 by right clicking on name and selecting rename, rename the processor to “nios_processor”
- Add the following connections by clicking on the circle to make it a filled in circle under the connections column
- Clock.clk connected to nios_processor.clk
- Clock.clk_reset connected to nios_processor.reset
- nios_processor.debug_reset_request connected to nios_processor.reset
- nios_processor.data_master connected to nios_processor.debug_mem_slave
- nios_processor.instruction_master connected to nios_processor.debug_mem_slave
- In the Ip Catalog in the left hand side navigate to Processors and Peripherals --> Embedded Processors --> Nios II Processor
- On Chip Memory
- Search in the top of the ip catalog to the left for “on chip” and selest the “On-Chip Memory (RAM or ROM)”
- Add this by double clicking it
- In the pop up select the following
- Type set to RAM (writable)
- Block Type set to AUTO
- Data width set to 32
- For the DE2-115 Total memory size 20400bytes (this is different per development board, consult your boards documentation)
- Have checked “initialize memory content”
- Click finish
- Rename the component to onchip_memory
- Make the following connections
- Clock.clk connect to onchip_memory.clk1
- nios_processor.data_master connect to onchip_memory.s1
- nios_processor.instruction_master connect to onchip_memory.s1
- Clock.clk_reset connect to onchip_memory.reset1
- nios_processor.debug_reset_request connect to onchip_memory.reset
- Set the base address to 0x000
- Lock the base address by clicking the lock icon and making it locked
- In the top navigation go to System --> Assign Base Addresses
- Jtag Uart
- Search in the top of the ip catalog to the left for “jtag” and select “JTAG UART”
- Add this by double clicking it
- In the pop up select the following for both Write and Read FIFO
- Buffer depth select 64
- irq threshold select 8
- Click finish
- Rename the component to jtag_uart
- Make the following connections
- Clock.clk connect to jtag_uart.clk
- Clock.clk_reset connec to jtag_uart.reset
- nios_processor.data_master connect to jtag_uart.avalon_jtag_slave
- ios_processor.debug_reset_request connect to jtag_uart.reset
- Connect the IRQ by clicking on the box in the IRQ column and set it to 8
- In the top navigation go to System --> Assign Base Addresses
- System ID or sysID
- Search in the top of the ip catalog to the left for “sysid” and select “System ID Peripheral”
- Add this by double clicking it
- In the pop up create a random hex number as the system ID
- Click finish
- Rename the component to sysid
- Make the following connections
- Clock.clk connect to sysid.clk
- Clock.clk_reset connec to sysid.reset
- nios_processor.data_master connect to sysid.control_slave
- ios_processor.debug_reset_request connect to sysid.reset
- Connect the IRQ by clicking on the box in the IRQ column and set it to 8
- In the top navigation go to System --> Assign Base Addresses
- Green LED’s PIO
- Search in the top of the ip catalog to the left for “pio” and select “PIO (Parallel I/O)”
- Add this by double clicking it
- In the pop up select the following
- Width to 8 bits
- Direction select Output
- Output Port Rest Value 0x00
- Rename the component to green_leds
- Make the following connections
- Clock.clk connect to green_leds.clk
- Clock.clk_reset connec to green_leds.reset
- nios_processor.data_master connect to green_leds.s1
- ios_processor.debug_reset_request connect to green_leds.reset
- Export the external connection by double clicking on the export column
- Name the export green_leds
- In the top navigation go to System --> Assign Base Addresses
- Save the system
- In the top navigation go to Generate --> Generate HDL...
- Choose Verilog
- Uncheck Create timing and resource estimates for third-party EDA synthesis tools
- Check Create block symbol file (.bsf)
- Select none for create symbol model
- Make sure the output path directory is the same as the project directory
- Click Generate
It is best practice to set your primary memory (the memeory you plan to run instuctions off to
both .data_master and .instruction_master and then set all other memeory just to .data_master
It is best practice to set the Jtag Uart IRQ to a least priority, you have 32 interrupts 0 being first priority and 32 being least priority
You must have a System ID of something other on 0 for the system to work in the Nios II development tools for eclipse
Note: Before Generating there must not be any errors or warnings in Qsys
Download Written Documentaion (PDF)
Download Quartus and Qsys Project Files (ZIP)